The present invention relates to a multiprocessor system comprising a plurality of central processing units (hereinafter abbreviated to CPUs) which are interconnected by common bus means, i.e. a data bus and an address bus, in which data transfer between the CPUs must be performed at arbitrary timings.
It is frequently necessary to form a multiprocessor system (i.e. a data processing system comprising a number of CPUs which normally function independently of one another) in which the CPUs may be interconnected by means of a common bus, and in which data must be transferred from one CPU to another at arbitrary timings. Various types of such system have been proposed in the prior art, as will subsequently be discussed in detail. However all of such prior art systems suffer from certain disadvantages. Basically, these disadvantages are that it is generally necessary for the system to ascertain the operation conditions of all of the CPUs in the system before implementing a transfer of data from one CPU to another. Another disadvantage, particularly in the case of a system in which such transfers are controlled through transfer commands originating in a command register, without using a common bus, then the command control circuitry becomes extremely complex as the number of CPUs in the system is increased. Another disadvantage, common to all of such prior art systems, is that it is generally necessary to alter the configuration of each CPU and of the data transfer control circuits whenever new CPUs are added to the system. It is therefore difficult to expand the number of CPUs in such a prior art multiprocessor system.
The above disadvantages of the prior art are overcome by the present invention, which provides a multiprocessor system comprising a plurality of CPUs interconnected by a common bus and enables data to be transferred between CPUs without affecting the operation of other CPUs, which utilizes very simple control circuitry, and which can be easily expanded by addition of CPUs without alteration to the existing CPUs or the control circuitry.